1. Field of the Invention
The present invention relates to high voltage vertical power transistors that are devices vertically formed on a silicon wafer (usually comprising an N-type epitaxial layer on an N.sup.+ substrate), the rear surface of which is connected to a high voltage. The invention relates to vertical power transistors of the MOS, bipolar or insulated-gate type, and more particularly relates to smart power switches that are circuits including, on a single silicon chip, vertical power components and logic circuits for controlling the power components.
2. Discussion of the Related Art
Power transistors are designed to withstand a definite forward voltage (for example 400 volts). If the external circuit applies a higher voltage, a damaging breakdown mode may occur. For example, the switching of an inductive load causes an overvoltage having a predetermined amount of energy that needs be dissipated. This overvoltage is applied onto the power switch which is off. One of the solutions to protect the device is to briefly set it in the conductive state for the time required to allow the excessive energy to flow through the device.
Therefore, it has been suggested to provide a device such as an avalanche diode that is set to a conductive state for a value slightly lower than the breakdown voltage of one or several power transistors, for example, to trigger the conductive state of such transistors before they reach their breakdown threshold, thus avoiding any damage.
FIG. 1, useful for understanding the problem that the invention aims to solve, is a cross-sectional view of a cell of an exemplary conventional dual structure including a vertical diffused power MOS (VDMOS) transistor TP. The VDMOS transistor is connected to logic circuits, an N-channel MOS transistor TL of which is schematically illustrated.
The structure is formed in a substrate 11 of a first conductivity type, for example of the N-type. A cell of the power MOS transistor TP includes a region 9-1, 9-2, formed by dopants of a second conductivity type, for example of the P-type. In each region 9-1, 9-2, are formed two N.sup.+ -type regions 14 which form the source of the power transistor. The two regions 14 are interconnected by a conductive layer 15 which is, for example, made of aluminum. The lateral edges of regions 9-1, 9-2 form a power transistor channel region 20.
Each cell of the power MOS transistor TP includes a gate 12 formed by a polysilicon layer. Gate 12 is separated from substrate 11 by an oxide layer 13.
The rear surface 17 of substrate 11 includes an overdoped layer 19 coated with a drain metallization 18.
The MOS transistor TL of the logic portion is formed in a P-type well 24. Well 24 includes two N.sup.+ -type diffusions. The first diffusion forms the source 22 and the second diffusion forms the drain 23 of transistor TL. Transistor TL includes a gate 21 formed by a polysilicon layer. Gate 21 is separated from well 24 by an oxide layer 25. Source 22 and drain 23 are respectively connected to a conductive line referenced 26, 27. Conductive lines 26, 27 are, for example, made of aluminum.
Conventionally, a P.sup.+ -type area 28 connected to a conductive layer 29 is provided in well 24. Area 28 and the conductive layer 29 connect well 24 to ground.
In normal operation mode, the rear surface metallization 18 is connected to a positive voltage and the front surface metallizations 15 of the power transistor are connected to voltages negative with respect to this positive voltage, for example voltages close to the ground voltage.
The problem to be solved is to prevent the power transistor from becoming conductive due to break down of the junction between substrate 11 and the P-type wells 9-1 and 9-2, i.e. when the drain voltage increases while the transistor is in the off state. Also, it should be noted, in the exemplary integrated circuit including a logic portion, that there is a risk that the junction, between the substrate and the wells in which are disposed the logic components, will break down.
To fabricate a diode capable of breaking down before the junction breaks down between substrate 11 and the wells, the diode can be vertically formed by providing in the N-type substrate a P-type region having a doping level selected so as to have a break down voltage lower than the junction between the substrate and the wells of the power transistors or of the logic portion. However, this would require an additional technological step in order to form this specifically doped P-type region. Despite the complexity of the process, the prior art approaches are directed to this method. However, the implementation of a diode on the front surface of the substrate makes it necessary to convey the high voltage available on the rear surface metallization to the front surface. Such method impairs the distribution of the field lines in the component while this distribution is carefully adjusted to provide the desired maximal breakdown (for example 400 volts, as indicated above).
U.S. Pat. Nos. 4,792,840 and 5,053,743 teach how to form, on the front surface of the substrate a resistor, a terminal of which is connected to the rear surface, the resistor being shaped like a spiral. However, none of these patents suggests that this technology can be extended to provide diodes.